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CS 665: Secure Memory Systems

  1. CS220 in Spring '18 or CS330 or CS422
  2. For M.Tech./M.S./Ph.D.: strong fundamentals in computer architecture and/or operating systems
  3. Good programming skills in C/C++
Course Objective

Memory subsystem is an important layer in the computing system that has to be efficient for the whole system to operate efficiently. In the current era of computation, multiple cores are deployed in devices that range from smart-phones, laptops, desktops, servers, and cloud based systems. Though, innovations in the world of hardware and computer architecture have resulted in faster computation in terms of better performance, a lot of sensitive data that is stored and processed by these devices can get leaked through various hardware components, such as branch predictors, caches, Translation look-aside buffers (TLBs), page tables, prefetchers, Dynamic Random Access Memory (DRAM) controllers, DRAM, and non-volatile memories (NVMs). Basically, these hardware components become side-channels and/or covert-channels and become source of information leakage in the form of side-channel and covert-channel attacks (for example, the recent meltdown and spectre attacks). The goal of the course is to make students understand the various sources of attacks and their mitigation techniques at the memory systems, and design secure memory systems. The course will be a fusion of fundamentals and state-of-the-art research on secure memory systems.

Course Contents

10K feet view: Spying on passwords through memory systems

The course comprises of four main modules apart from a module on preliminaries.

  1. Module 0: Preliminaries on Caches, DRAM, and Virtual memory systems
  2. Module 1: Secure Caches
    1. Side-channel and covert-channel attacks at different levels of cache hierarchy
    2. Cache attack mitigation techniques
    3. Trade-off between system performance, power, and security
  3. Module 2: Secure DRAMs
    1. Side-channel and covert-channel attacks at the DRAM controllers
    2. Side-channel and covert-channel attacks at the DRAM chips
    3. Attack mitigation techniques
  4. Module 3: Secure Virtual Memory Systems
    1. Side/covert-channel attacks at the TLBs, MMU caches, Page-table walkers
    2. Mitigation techniques at different levels of virtual memory system
  5. Module 4: Other Topics
    1. Reverse engineering memory systems
    2. Interface between secure memory system, secure processor, and secure OS. Intel SGX, ORAMs
    3. Security issues in NVMs
Guest Lectures
  1. Clementine Maurice
  2. Vinod Ganapathy