Seminar by Rahul Nagpal
Compiler-Assisted Energy Optimization for Clustered VLIW Processors
Rahul Nagpal
Indian Institute of Science
Date: Wednesday, September 9, 2009
Time: 5:00 PM
Venue: CS102.Abstract:
Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. Inter-cluster communication introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units and other data-path components.
In the past, study of leakage energy management at the architectural level has mostly focused on storage structures such as cache. Relatively, little work has been done on architecture level leakage energy management in functional units in the context of superscalar processors and energy efficient scheduling in the context of VLIW architectures. In the absence of any high level model for interconnect energy estimation; the primary focus of research in the context of interconnects had been to reduce the latency of communication and evaluation of various inter-cluster communication models.
In this talk, I will discuss scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low power modes of interconnects and functional units with little performance loss. I will also present a high level model for the estimation of interconnect delay and energy (in contrast to lower level circuit level models proposed earlier) that makes it possible to perform architectural and compiler optimization targeting interconnects.
If time permits, I will briefly discuss power-performance optimization in the context of other decentralized architectures such as SpMT architectures.
About The Speaker:
Rahul Nagpal received his MS degree and PhD in Computer Science from Indian Institute of Science in 2004 and 2008 respectively. His primary research interest is in the area of compiler assisted performance and power optimization for decentralized architectures with a special focus on clustered and multi-core architectures.