Seminar by Mr. Anand Moghe
Adavances in VLSI Designs for Testability
Mr. Anand Moghe
Senior Engineering Manager
Mentor Graphics India Pvt. Ltd., Hyderabad
Part I
Date: Wed, April 11, 2005
Time: 5:00 PM
Venue: CS-101
Part II
Date: Thu, April 12, 2005
Time: 8.00 AM
Venue: CS-101
Abstract
The main purpose of the test process, as it is applied to the manufacturing of semiconductor devices is to provide a measure of the quality and/or reliability of a finished semiconductor product. The purpose for Design-for-test (DFT) is to place "hardware hooks" on the die to enable conducting the quality-reliability measurement. If done correctly DFT will: Enable the quality goals to be met with a high degree of confidence (fault coverage) during testing. Allow the coverage measurement to be done efficiently and economically to meet the cost-of-test goals. Enable some form of test vector automation, such as ATPG. The talk aims at covering the fundamental philosophy of test, the different types of fault models used by the software tools and the Automatic Test Pattern Generation (ATPG) process. It will also mention about the ATPG algorithms and fault simulation. The popular structured test methodologies such as Full-scan, Built-In-Self-Test (BIST) for memory and logic, Boundary Scan, etc., will be discussed. Finally, some commercially available test tools, and a few recent announcements from some of the DFT tool vendors will be mentioned.
About the Speaker
Anand Moghe has a rich experience in VLSI designs for testability (DFT). He has been managing the technical development of Mentor's flagship products in the area of DFT. Some of the Mentor's tools in this are are MBIST (Memory built-in self test) and LBIST (logic BIST).