Seminar by Prof. Shashank K Mehta
Synthesis of Sequential Circuits with Clock-Control to Improve Testability
Shashank K Mehta
Kanwal Rekhi School of Information Technology
Indian Institute of Technology Bombay
Date: August 15, 2001
Time: 03:30 PM
Venue: CC-217
Abstract
A test-vector sequence for a sequential circuit can be viewed as a sequence of subsequences each of which has three tasks. Justification: moving from the last state to the state where next test can be applied, Test: application of the test pattern, Propagation: leading the erroneous signal to a primary output. A scan-capable circuit can perform justification (step 1) in log N (N = number of states) steps and propagate in one step. In functional testing, passage into illegal states is not allowed so scan cannot be used. In this situation a poorly connected Finite-State-Machine can, in the worst case, require O(N) steps for justification.
In this talk we will discuss a method to improve the graph connectivity by controlling the clock without modifying the underlying FSA of the circuit. I will present a state-encoding scheme which, in conjunction with the clock-control, has O(log N) time bound for justification without entering an illegal state.
About the Speaker
Prof. Shashank K Mehta received his MSc (Physics) and MTech (CS) from IIT Kanpur. He did his PhD from University of Nebraska. In 1986, he joined Rensslaer Polytechnic Institute as Assistant Professor, and was there till 1990. From 1990 to 2001, he was Reader in CS Department at Pune University. Recently he has joined KR School of Information Technology at IIT Bombay He has been working in VLSI testing for past 6 years. Lately, he has also been working in Algebraic Geometry with the objective of applying it to the areas such as test-generation, model-checking, etc. He is also very much interested in Graph Theory and Category Theory.
Prof. Shashank K Mehta is a candidate for faculty position in the CSE department.