Seminar by Prof. Sunil Khatri
Analysis and Avoidance of Cross-talk in On-chip Buses
Sunil Khatri
Department of Electrical and Computer Engineering
University of Colorado at Boulder
Date: August 13, 2001
Time: 03:30 PM
Venue: CC-217
Abstract
We present techniques to analyze and alleviate cross-talk in on-chip buses. With rapidly shrinking process feature sizes, wire delay is becoming a large fraction of the overall delay of a circuit. Additionally, the increasing cross-coupling capacitances between wires on the same metal layer create a situation where the delay of a wire is strongly dependent on the electrical state of its neighboring wires. The delay of a wire can vary widely depending on whether its neighbors perform a like or unlike transition. This effect is acute for long on-chip buses. In this work, we classify cross-talk interactions between the wires of an on-chip bus. We present encoding techniques which can help a designer trade off cross-talk against area overhead. Our experimental results show that the proposed techniques result in reduced delay variation due to cross-talk. As a result, the overall delay of a bus actually decreases even after the use of the encoding scheme.
In the later part of the talk, I will briefly describe other research being conducted in the VLSI and other research groups at CU Boulder.
About the Speaker
Sunil P Khatri graduated from the EE department of IIT Kanpur in 1987. He received his MS in ECE from the University of Texas, Austin in 1989. For the next 4 years, he worked at Motorola, Inc with the MC 88110 RISC microprocessor and PowerPC 603 development teams. In 1993, he joined the CAD research group at UC Berkeley, working under Profs Brayton and Sangiovanni-Vincentelli. After receiving his PhD in 1999, he joined the ECE faculty at the University of Colorado, Boulder in Jan 2000. His research interests include VLSI design and VLSI design and layout automation. Specific topics include high-speed switch-level simulation, exploiting and analysis of cross-talk in DSM IC design, datapath design automation, SOI design, high-speed IO interfaces, mixed-signal and digital testing, layout fabrics for DSM IC design, VLSI routing, timing analysis in the presence of cross-tlak, ROBDDs, combinational verification, multi-valued logic, hierarchical synthesis.