Publications
Microarchitecture for Security
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[DATE 2021
] Vishal Gupta, Vinod Ganesan, and Biswabandan Panda, “ Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks ” in Proceedings of 25th IEEE/ACM Design and Automation Test in Europe, 2021
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[DABANGG Attack ] Anish Saxena and Biswabandan Panda, “DABANGG: Time for Fearless Flush based Cache Attacks”
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[SILM@EuroS&P 2020 ] Aditya Rohan, Biswabandan Panda, Prakhar Agarwal, “Reverse Engineering the Stream Prefetcher for Profit”, in Proceedings of SILM Workshop on Security of Software/Hardware Interfaces@5th European Symposium on Security and Privacy, Genova, Italy, 2020.
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[PACT 2019 ] Biswabandan Panda, “Fooling The Sense of Cross-core Last-level Cache Eviction Based Attacker By Prefetching Common Sense”, in Proceedings of 28th International Conference on
Parallel Architectures and Compilation Techniques, Seattle, USA, 2019.
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[WOOT19@USENIXSEC-2019
]Dixit Kumar, Chavhan Sujeet Yashavant, Biswabandan Panda, and Vishal Gupta “How Sharp is SHARP?” -
[HASP@ISCA-2019
] Santhosh Kumar T, Debadatta Mishra, Biswabandan Panda, Nayan Deshmukh, “CoWLight: Hardware Assisted Copy-On-Write Fault Handling for Secure Deduplication”
Microarchitecture for Performance
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[IPC1@ISCA-2020
] Vishal Gupta, Neelu Shivprakash Kalani, and Biswabandan Panda, “Run-Jump-Run: Bouquet of Instruction Pointer Jumpers for High Performance Instruction Prefetching” -
[ISCA 2020
] Samuel Pakalapati and Biswabandan Panda, “Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching”, In Proceedings of the 47th International Symposium on Computer Architecture, Valencia, Spain [virtual one], 2020 [ Source code] -
[DPC3@ISCA-2019
] Samuel Pakalapati and Biswabandan Panda, “Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Hardware Prefetching” [Winner of the Championship ] -
[CVP@ISCA2018
] Arpit Gupta, Parv Mor, Hrithvik Taneja, and Biswabandan Panda, “STEVES: Pushing the Limits of Value Predictors with Sliding FCM and EVES” [Leading the leaderboard in the unlimited track]
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[CVP-1 @ISCA '18
] Nayan Deshmukh*, Snehil Verma*, Prakhar Agrawal*,
Biswabandan Panda, and Mainak Chaudhuri, “DFCM++: Augmenting DFCM with Early Update and Data Dependence-driven
Value Estimation”, In Value Prediction Championship(CVP-1), 2018.
[ICCD 2017 ] Dennis Antony Varkey, Biswabandan Panda, and Madhu Mutyam, “RCTP: Region Correlated Temporal Prefetcher ”, In Proceedings of 35th IEEE International Conference on Computer Design, Boston, USA, 2017.
Hardware Data Compression
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[PACT 2018
] Biswabandan Panda and André Seznec, “Synergistic Cache Layout for Reuse and Compression”, in Proceedings of 27th International Conference on
Parallel Architectures and Compilation Techniques, Limassol, Cyprus, 2018. -
[ACM TACO 2017/HiPEAC 2018
] Kanakagiri Raghavendra, Biswabandan Panda, and Madhu Mutyam, “MBZip: Multi-Block Data Compression”, In ACM Transactions on Architecture and Code Optimization, 2017. -
[MICRO 2016
] Biswabandan Panda and André Seznec, “Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches”, In Proceedings of 49th IEEE/ACM International Symposium on Microarchitecture, Taipei, Taiwan, 2016. -
[IEEE TC 2016
] Kanakagiri Raghavendra, Biswabandan Panda, and Madhu Mutyam, “PBC: Prefetched Blocks Compaction”, In IEEE Transactions on Computers, 65 (8), 2016 (accepted in 2015 and published in 2016). -
[PACT 2015 poster
] Kanakagiri Raghavendra, Biswabandan Panda, and Madhu Mutyam, “MBZip: A Case for Compressing Multiple Data Blocks”, In 24th ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques, San Francisco, 2015.
Prefetcher Aggressiveness Controllers
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[ACM TACO 2017
] Aswin Sridharan, Biswabandan Panda, and André Seznec, “ Band-pass Prefetching: An Effective Prefetch Management Mechanism using Prefetch-fraction in Multicore Systems ”, In ACM Transactions on Architecture and Code Optimization, 2017. -
[IEEE TC 2016
] Biswabandan Panda, “SPAC: A Synergistic Prefetcher Aggressiveness Controller for Multi-core Systems”, In IEEE Transactions on Computers, 65 (12), 2016. -
[IEEE CAL 2016
] Biswabandan Panda and Shankar Balachandran, “Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers”, In IEEE Computer Architecture Letters, 15 (1), 2016 (accepted in 2015 and published in 2016). -
[ACM TACO 2015/HiPEAC 2016
] Biswabandan Panda and Shankar Balachandran, “CAFFEINE: A Utility-driven Prefetcher Aggressiveness Engine for Multicores”, In ACM Transactions on Architecture and Code Optimization, 12 (3), 2015. -
[DATE 2014
] Biswabandan Panda and Shankar Balachandran, “Introducing Thread Criticality Awareness in Prefetcher Aggressiveness Control”, In Proceedings of 17th IEEE/ACM International Conference on Design, Automation & Test in Europe, Dresden, Germany, 2014 -
[PACT 2013 poster
] Biswabandan Panda and Shankar Balachandran, “TCPT - Thread Criticality-driven Prefetcher Throttling”, In Proceedings of 22nd ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, Scotland, 2013. -
[PACT 2014
] Biswabandan Panda and Shankar Balachandran, “XStream: Cross-core Spatial Streaming based MLC Prefetchers for Parallel Applications in CMPs”, In Proceedings of 23rd IEEE International Conference on Parallel Architectures and Compilation Techniques, Edmonton, Canada, 2014. -
[PACT 2012 poster
] Biswabandan Panda and Shankar Balachandran, “Hardware Prefetchers for Emerging Parallel Applications”, In Proceedings of 21st ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques, Minneapolis, USA, 2012. (One of the 6 posters selected for final presentation round)
Others
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[CANS 2020 ] Saurabh Kumar, Debadatta Mishra, Biswabandan Panda and Sandeep Shukla, “STDNeut: Neutralizing Sensor, Telephony System and Device State Information on Emulated Android Environments ”, In Proceedings of 19th International Conference Cryptology and Network Security, Vienna, Austria, 2020
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[SBAC-PAD 2012 ] Biswabandan Panda and Shankar Balachandran, “CSHARP - Coherence and SHaring Awareness Replacement Policies for Parallel Applications”, In Proceedings of 24th IEEE International Conference on Computer Architecture and High Performance Computing, New York, USA, 2012