Source code for L1 instruction cache prefetchers

Source code for L1 instruction cache prefetchers with parameters tuned for IPC-1 (the 1st Instruction Prefetching Championship) configuration Code for PTBbr prefetcher Code for PTBbr with PTB microarchitecture details Code for PTBcl prefetcher Code for next-2-line (Next2L) prefetcher Code for return address stack-directed prefetching (RDIP) Code for proactive instruction fetching (PIF) Code for PIF+ghist Reference: Synthesizing Code Prefetchers from Control Speculation Hardware. May 2020. [PDF]