The course comprises of four main modules apart from a module on preliminaries.
- Module 0: Preliminaries on Caches, DRAM, and Virtual memory systems
(Depends on the dynamics of the class)
- Module 1: Secure Caches
(i) Side-channel and covert-channel attacks at different levels of cache hierarchy
(ii) Cache attack mitigation techniques
(iii) Trade-off between system performance, power, and security
- Module 2: Secure DRAMs
(i) Side-channel and covert-channel attacks at the DRAM controllers
(ii) Side-channel and covert-channel attacks at the DRAM chips
(iii) Attack mitigation techniques
- Module 3: Secure Virtual Memory Systems
(i) Side/covert-channel attacks at the TLBs, MMU caches, Page-table walkers
(ii) Mitigation techniques at different levels of virtual memory system
- Module 4: Other Topics
(i) Reverse engineering memory systems
(ii) Interface between secure memory system, secure processor, and secure OS. Intel SGX,
ORAMs
(iii) Security issues in NVMs