"A Fault-tolerant Array Processor Designed for Testability and Self-Reconfiguration", A.Jain, B.Mandava,J.Rajski, N.C.Rumin, IEEE Journal of Solid State Circuits, May 1991, pp778-788.
"Emerging Trends in Machine Translation between English and Indian Languages", R.Jain, R.M.K.Sinha, A.Jain, Journal of Computer Science and Informatics, March 1997, pp 19-25.
"Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms", V.Rajesh, Ajai Jain, VLSI DESIGN'98, 11th International Conference on VLSI Design, Chennai, January 4-7, 1998, pp 270-273.
"Testability Preserving and Enhancing Transformations for Robust Delay Fault Testability", Amey Karkare, Manoj Singla, Ajai Jain, VLSI DESIGN'98, 11th International Conference on VLSI Design, Chennai, January 4-7, 1998, pp 370-373.
"Application of Genetic Algorithm to Automatic Test Pattern Generation", Ajai Jain, Salil Prabhakar, 5th International Conference on Advanced Computing, Chennai, December 15-17, 1997, pp 295-301.
"Modular Fault-Tolerant Hypercube", Ajai Jain, Ajit Bannerjee, 5th International Conference on Advanced Computing, Chennai, December 15-17, 1997, pp 475-482.
"Test-Generation for Sequential Circuits using Bus-Fault Model", D.R.Chakrabarty, A.Jain, VLSI'96, International Conf. of VLSI Design, Bangalore, Jan. 3-6, 1996 pp174-177.
"Design of a Parallel Processor for NLP Applications", P.Sukumar, A.Jain, International conference on Information, Systems Analysis Synthesis,Orlando, U.S.A., July 22-26, 1996.
"Machine Translation using Examples for Similar and Dissimilar Languages", R.Jain,R.M.K.Sinha, A.Jain, International conference on Information, Systems Analysis Synthesis,Orlando, U.S.A., July 22-26, 1996.
"Relevance and strategies of MT in Global Environment and Integrated Approach to MT in Indian context", R.M.K.Sinha, A.Jain, Conference of Society of Machine Aided Translation, SMATAC'96, New Delhi.
"Some Experiences on Anglabharti an Anubharti Projects", Renu Jain, R.M.K.Sinha, A.Jain, R.P.Shukla, U.Tewari, Conference of Society of Machine Aided Translation, SMATAC'96, New Delhi.
"On Multilingual Dictionary Design - English to Indian Languages", R.M.K.Sinha, A.Jain, Conference of Society of Machine Aided Translation, SMATAC'96, New Delhi.
"A Pattern-Directed Hybrid Approach to Machine Translation Through Examples", R.Jain, R.M.K.Sinha, A.Jain, SNLP'95 : 2nd Symp. on Natural Lang. Processing, Bangkok, Thailand, August 2-4, 1995, pp 324-335.
"HFSM : A Finite State Machine for Analyzing Hindi Sentences", R.Jain, R.M.K.Sinha, A.Jain, R.Srivastava, SNLP'95 : 2nd Symp. on Natural Lang. Processing, Bangkok, Thailand, August 2-4, 1995, pp 317-322.
"Role of Examples in Translation", R.Jain, R.M.K.Sinha, A.Jain, '95 IEEE Conf. on Systems, Man and Cybernetics, Vancouver, Canada, Oct 22-25, 1995, pp 1615-1620.
"ANGLABHARTI: A Multilingual Machine Aided Translation Project on Translation from English to Indian Languages", R.M.K.Sinha, K.Sivaraman, A.Agrawal, R.Jain, R.Srivastava, A.Jain, '95 IEEE Conf. on Systems, Man and Cybernetics, Vancouver, Canada, Oct 22-25, 1995, pp 1609-1614.
"An Improved Hierarchical Test Generation Technique for Combinational Circuits with Repetitive Sub-circuits", D.R. Chakrabarty, A. Jain, 4th Asian Test Conference (ATS'95), Bangalore, Nov. 23-24, 1995, pp 237-244.
"On the Monotonicity of Yield of Fault- Tolerant Reconfigurable Multi-pipeline Structures", A.Jain, 2nd Australasian Conf. on Parallel and Real Time Systems, Sept. 28-29, 1995, Fremantle, Western Australia, pp 296-303.
"Analyzing Logical Properties of Reconfigurable Processor Arrays", A.Jain, First Conference on Fault Tolerant Computing, Madras, Dec. 20-22, 1995, pp 180-189.
"Fault Diagnosis and Tolerance in Repetitive Circuits"' D.R.Chakrabarty, A.Jain, First Conference on Fault Tolerant Computing, Madras, Dec. 20-22, 1995, pp 107-113.
"An Efficient Algorithm for Fault-tolerance Through Reconfiguration in VLSI Arrays", Ajai Jain, Praerit Garg, Proceedings of Seminar on Electronic Systems and Applications, Roorkee, March 30-31, 1994, pp 261-269.
"Design of High-Speed Fault-Tolerant Arithmetic Unit for VLSI Implementation", Ajai Jain, Ravi Pinnamaneni, Proceedings of Seminar on Integrated Electronics, Roorkee, March 20-21, 1993, pp- 61-70.
"Probabilistic analysis of yield and area utilization of reconfigurable rectangular Processor Arrays", A.Jain,J.Rajski, International Workshop on Defect and Fault Tolerance in VLSI Systems, , Springfield, Massachuttes, U.S.A., Oct 1988.
"A Processing Element for a Reconfigurable Massively Parallel Processor", H.Cox, A.Jain,et al., Canadian Conference on VLSI (CCVLSI),, Oct. 1987, pp-241-246.
Ajai Jain and Janusz Rajski, 'Probabilistic Analysis of Yield and Area Utilization of Reconfigurable Rectangular Processor Arrays', Chapter in the book 'Defect and Fault Tolerance in VLSI Systems', edited by I.Koren, Published by Plenum Publishers, New York.